/* Boards included:
	a2
	a5
	a7
*/

/*
#define SERIAL_STRING		Ambarella
#define SERIAL_NUMBER		1000
#define SERIAL_INCREASE_SETP	1
#define VERSION_TYPE		pri
*/
#define MAC1 dev.eth[0].mac
#define MAC2 dev.wifi[0].mac
#define MAC3 dev.usb_eth[0].mac
//wait programming time(ms): NAND use default 0
#define PROGRAM_TIMEOUT 30000000

/* Sync on 2009/05/27 (a2sbub_20) */
[a2]
#define ARCH_VER		2100
#define DEFAULT_DRAM_FREQ	216
#define DRAM_SIZE		0x08000000	/* 1024 Mbit */
#define DRAM_CFG_VAL		0x1000000a
#define DRAM_EXT_MODE_VAL	0x00000004

#define DRAM_MODE____108MHZ	0x00001452
#define DRAM_TIMING1_108MHZ	0x22524d26
#define DRAM_TIMING2_108MHZ	0x00000026
#define DRAM_REF_CTL_108MHZ	0x0000883b

#define DRAM_MODE____135MHZ	0x00001452
#define DRAM_TIMING1_135MHZ	0x22524d26
#define DRAM_TIMING2_135MHZ	0x00000026
#define DRAM_REF_CTL_135MHZ	0x0000883b

#define DRAM_MODE____148MHZ	0x00001452
#define DRAM_TIMING1_148MHZ	0x22524d26
#define DRAM_TIMING2_148MHZ	0x00000026
#define DRAM_REF_CTL_148MHZ	0x0000883b

#define DRAM_MODE____162MHZ	0x00001452
#define DRAM_TIMING1_162MHZ	0x22524d26
#define DRAM_TIMING2_162MHZ	0x00000026
#define DRAM_REF_CTL_162MHZ	0x0000883b

#define DRAM_MODE____189MHZ	0x00001452
#define DRAM_TIMING1_189MHZ	0x22524d26
#define DRAM_TIMING2_189MHZ	0x00000026
#define DRAM_REF_CTL_189MHZ	0x0000883b

#define DRAM_MODE____216MHZ	0x00001652
#define DRAM_TIMING1_216MHZ	0x365b663a
#define DRAM_TIMING2_216MHZ	0x0000002a
#define DRAM_REF_CTL_216MHZ	0x00008d2f

#define DRAM_MODE____243MHZ	0x00001652
#define DRAM_TIMING1_243MHZ	0x3c5b763a
#define DRAM_TIMING2_243MHZ	0x0000002c
#define DRAM_REF_CTL_243MHZ	0x00008ed3

#define RCT_DLL0_108MHZ		0x00100620
#define RCT_DLL1_108MHZ		0x00100620
#define RCT_DLL0_135MHZ		0x00100620
#define RCT_DLL1_135MHZ		0x00100620
#define RCT_DLL0_148MHZ		0x00100620
#define RCT_DLL1_148MHZ		0x00100620
#define RCT_DLL0_162MHZ		0x00100620
#define RCT_DLL1_162MHZ		0x00100620
#define RCT_DLL0_189MHZ		0x00100620
#define RCT_DLL1_189MHZ		0x00100620
#define RCT_DLL0_216MHZ		0x00100620
#define RCT_DLL1_216MHZ		0x00100620
#define RCT_DLL0_243MHZ		0x00100620
#define RCT_DLL1_243MHZ		0x00100620

#define RCT_DLL_CTRL_SEL_VAL	0x00005ef2
#define RCT_DLL_OCD_BITS_VAL	0x00010202

#define DEFAULT_GPIO1_AFSEL	0xfbffffff
#define DEFAULT_GPIO1_DIR	0xfbffffff
#define DEFAULT_GPIO1_MASK	0x04000000
#define DEFAULT_GPIO2_AFSEL	0xfffffffe
#define DEFAULT_GPIO2_DIR	0xfffffffe
#define DEFAULT_GPIO2_MASK	0x00000001

/* Sync to 2009/8/14 */
[a5]
#define ARCH_VER		5100
#define BSP_INI			"sv\a5s\a5s_gopro_hd2.ini"

#define DEFAULT_GPIO0_AFSEL    	0xfffdc1ff
#define DEFAULT_GPIO0_DIR	0x00000000
#define DEFAULT_GPIO0_MASK    	0x00000000
#define DEFAULT_GPIO0_DATA    	0x00000000
#define DEFAULT_GPIO1_AFSEL    	0xffffffff
#define DEFAULT_GPIO1_MASK    	0x00000000
#define DEFAULT_GPIO1_DIR	0x00000000
#define DEFAULT_GPIO1_DATA	0x00000000
#define DEFAULT_GPIO2_AFSEL    	0xffffffff
#define DEFAULT_GPIO2_DIR    	0x00000000
#define DEFAULT_GPIO2_MASK	0x00000000
#define DEFAULT_GPIO2_DATA    	0x00000000
#define DEFAULT_GPIO3_AFSEL    	0x00000000
#define DEFAULT_GPIO3_DIR	0x00000000
#define DEFAULT_GPIO3_MASK    	0x00000000
#define DEFAULT_GPIO3_DATA    	0x00000000

/* Sync to 2011/4/27 */
[a7]
#define ARCH_VER		7500
#define BSP_INI			"sv\a7l\bst_a7lbub.ini"

#define DEFAULT_GPIO0_AFSEL     0xfffdc1ff
#define DEFAULT_GPIO0_DIR       0x00000000
#define DEFAULT_GPIO0_MASK      0x00000000
#define DEFAULT_GPIO0_DATA      0x00000000
#define DEFAULT_GPIO1_AFSEL     0xffffffff
#define DEFAULT_GPIO1_MASK      0x00000000
#define DEFAULT_GPIO1_DIR       0x00000000
#define DEFAULT_GPIO1_DATA      0x00000000
#define DEFAULT_GPIO2_AFSEL     0xffffffff
#define DEFAULT_GPIO2_DIR       0x00000000
#define DEFAULT_GPIO2_MASK      0x00000000
#define DEFAULT_GPIO2_DATA      0x00000000
#define DEFAULT_GPIO3_AFSEL     0xffffffff
#define DEFAULT_GPIO3_DIR       0x00000000
#define DEFAULT_GPIO3_MASK      0x00000000
#define DEFAULT_GPIO3_DATA      0x00000000


/* Default GPIO IO PAD control setting */
#define DEFAULT_GPIO0_CTRL_ENA	0x00000000
#define DEFAULT_GPIO0_CTRL_DIR	0x00000000
#define DEFAULT_GPIO1_CTRL_ENA	0x00000000
#define DEFAULT_GPIO1_CTRL_DIR	0x00000000
#define DEFAULT_GPIO2_CTRL_ENA	0x00000000
#define DEFAULT_GPIO2_CTRL_DIR	0x00000000
#define DEFAULT_GPIO3_CTRL_ENA	0x00000000
#define DEFAULT_GPIO3_CTRL_DIR	0x00000000
#define DEFAULT_GPIO4_CTRL_ENA	0x00000000
#define DEFAULT_GPIO4_CTRL_DIR	0x00000000
#define DEFAULT_GPIO5_CTRL_ENA	0x00000000
#define DEFAULT_GPIO5_CTRL_DIR	0x00000000